The present invention relates to a domino-type MOS logic gate including a logic network comprising MOS transistors of a first conductivity type receiving input data and being connected between a first and a second voltage source via a source-drain path of a MOS precharging transistor of a second conductivity type, and a MOS validation transistor of the first conductivity type, respectively, a control electrode of the precharging and of the validation transistor receiving both a clock signal which, when it is at a first logic level, precharges at a precharging level an output of the logic gate and when it is at a second logic level allows reading of a logic output signal at the output.
In U.S. Pat. No. 3,551,693 the clock signal is used to provide a precharging of the output of the logic gate. Actually, when the clock signal is at a low level, said precharging transistor, which in the prior art is of the p-MOS type, is conductive and said validation transistor, which in the prior art is of the n-MOS type, is non-conductive, which causes the output of the logic gate to be precharged to the high level. When the clock signal is at the high level, the n-MOS validation transistor is conductive and the p-MOS precharging transistor is non-conductive. In that case, when the logic network is in a conductive state, the output of the logic gate changes state to the low level, while it remains at the high level when the logic network is not in a conductive state. The correct operation of the logic MOS gate implies that the data are stabilized at each clock pulse before the clock signal rises to the high level. Actually, when the changing of state of a data is effected with a delay and when this has for its consequence that the logic network is maintained incorrectly in a conducting state during a certain period of time, the effect of precharging the output to the high state may be completely or partly lost, and the output of the logic gate may remain at the low level when the logic network has become non-conductive.